Field of the Invention
The invention relates to a RAM memory circuit and method for controlling the RAM memory circuit having a multiplicity of memory cells and having addressing and control devices for accessing the memory cells for writing in and reading out data. The memory cells are disposed in a matrix form in rows and columns and each are addressed for the process of writing in or reading out a datum by activation of a word line associated with the relevant row and connection of a sense amplifier associated with the relevant column to a data path. A preferred area of application is dynamic RAMs (DRAMS), in particular, synchronous DRAMs (SDRAMs, DDR-RAMS or RDRAMs).
Dynamic random access memories, as are generally known by the acronym DRAM, contain one or more arrays or banks of memory cells that are in each case disposed in the manner of a matrix in rows and columns. Each row is assigned a row selection line, referred to as xe2x80x9cword linexe2x80x9d and each column is assigned a column selection line, which is referred to as xe2x80x9cbit linexe2x80x9d and is usually configured in two-core fashion (xe2x80x9cbit line pairxe2x80x9d). Each memory cell includes, in addition to a capacitor that forms the actual memory element and whose respective state xe2x80x9cchargedxe2x80x9d or xe2x80x9cunchargedxe2x80x9d represents the binary or logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d of the stored datum, a selection transistor that can be turned on by activation of the relevant word line. With the selection transistor in the on state, the capacitor is connected to the bit line pair to transfer the charge of the capacitor onto the bit line pair so that the stored datum can be sensed as a potential difference on the bit line pair. For sensing and evaluating the potential difference, each bit line pair is assigned a sense amplifier that is latched into a defined first or second state, depending on whether the sensed potential difference corresponds to the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d of the stored datum.
For a selective access to selected memory cells, first, a selected word line is activated by application of an activation potential (usually so-called xe2x80x9cHxe2x80x9d potential, which is positive with respect to the zero potential). The word line to be activated is selected depending on a row address provided, which is decoded in a row decoder. With the word line activation, the selection transistors of all the memory cells of the addressed row are turned on so that the potential differences that indicate all the data of the addressed row build up on the bit line pairs of all the columns. These data are latched in the assigned sense amplifiers. This latching operation has the effect that the sensed data are written back to the respective memory cells in amplified and, thus, refreshed form and, moreover, are ready for fetching in the sense amplifiers.
After this state has been reached, what conventionally follows is the further control of the DRAM for reading or writing, the sense amplifiers being selectively connected to a data path by actuation of selected transfer switches in order either to read out the latched data from the DRAM through the data path (read cycle) or to overwrite the data by new data (write cycle). This xe2x80x9ccolumnxe2x80x9d selection is effected by selection of the transfer switches to be actuated depending on column select signals based upon column addresses that are decoded in a column decoder.
Starting from the command that initiates the activation of the selected word line, it takes a certain period of time for the sense amplifiers to reach their final state. First, it is necessary for the applied activation potential to develop along the word line until the selection transistors in the memory cells respond. Then a certain period of time elapses until the bit line pairs have accepted the charge of the memory cells and the sense amplifiers can be switched on to be driven into their latching state. Only afterward are the latched data released for read-out or overwriting. The minimum waiting time to be complied with between a word line activation command, and the start of each read or write cycle is defined in the context of the customary specification of a DRAM and, naturally, restricts the operating speed of the memory circuit.
It is accordingly an object of the invention to provide a RAM memory circuit and method for controlling the RAM memory circuit that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that reduces the sum of the waiting times during the operation of a DRAM and, thereby, increases the average operating speed.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a RAM memory circuit, including a multiplicity of memory cells disposed in matrix form in rows and columns, the cells storing datum, the rows having row addresses, the columns having column addresses, word lines each being associated with a respective one of the rows, sense amplifiers each being associated with a respective one of the columns, data input/output means, a data path connected to the sense amplifiers and to the data input/output means for transferring data in either direction between the sense amplifiers and the data input/output means, each of the memory cells being addressable for writing in or reading out a datum by activation of the one word line associated with a respective one of the rows and by connecting a sense amplifier associated with a respective one of the columns to the data path, an addressing device having a row decoder connected to the word lines for selecting the word line to be activated dependent upon a provided row address and a column decoder connected to the sense amplifiers for selecting respective ones of the sense amplifiers to be connected to the data path dependent upon the column addresses provided thereto, and a control device connected to the word lines, the control device activating a selected one of the word lines and subsequently initiating a connection of the selected sense amplifiers to the data path, the control device, upon receiving an immediate-write command, being set to command a write operation to initiate a connection of the sense amplifiers selected by the column address provided to the data path at an instant ta+Tw, where ta is an instant of an activation of the word line selected by the provided row address and Tw is less than a charging time necessary, starting from the word line activation, to transfer the datum stored in one of the memory cells of the respective one of the rows to the respectively selected sense amplifier and to amplify the datum at the respectively selected sense amplifier.
Accordingly, the invention is realized on a RAM memory circuit that contains the following: a multiplicity of memory cells, which are disposed in matrix form in rows and columns and can each be addressed for the process of writing in or reading out a datum by activation of a word line assigned to the relevant row and connection of a sense amplifier assigned to the relevant column to a data path, an addressing device with a row decoder for the selection of the word line to be activated depending on a row address provided, and with a column decoder for the selection of the sense amplifiers to be connected to the data path depending on column addresses provided; a control device that is configured for the activation of the selected word line and for the subsequent initiation of the connection of the selected sense amplifiers to the data path. According to the invention, the control device can be set by an immediate-write command, which commands the write operation, such that it initiates the connection of the sense amplifiers selected by the column addresses provided to the data path at an instant ta+Tw, where ta is the instant of the activation of the word line (WL) selected by the row address provided and Tw is less than the charging time Tc that is specific to the memory circuit and is necessary, starting from a word line activation, in order to transfer the datum stored in a memory cell of the relevant row to the respectively selected sense amplifier and to amplify it there.
The invention is based on the insight that, for writing data at memory cells of a selected row, it is not actually necessary to wait, after the activation of the relevant word line, until the sense amplifiers of those columns in which the relevant memory cells are located have reached their state that evaluates and latches the previous datum. This means that sense amplifiers that are intended to receive write data can be switched on practically at the same time as the activation of the word line, and that the column selection can begin without delay to connect the sense amplifiers to the data path carrying the write data and to write the data at the relevant memory cells without delay. Although this saving of waiting time only takes place during writing, the overall result is an increase in the average operating speed, particularly if there is frequent alternation between reading and writing during the operation of the memory, that is to say, a frequent initiation of write cycles has to take place.
A further advantage of the invention is that, by virtue of the advanced beginning of the write cycle, not only waiting time but also current is saved because the current-wasting charging of the bit lines and driving of the sense amplifiers to the previously stored data values are obviated.
To be able to optimally utilize the possibility of the brought-forward beginning of a write cycle, the addressing device of the RAM must be configured such that it provides the column addresses in valid fashion, and decodes them, as early as possible before the charging time Tc has elapsed. In the case of the DRAMs sold under the proprietary name xe2x80x9cRDRAMxe2x80x9d by the company Rambus Inc., this can easily be realized because, in this case, row and column addresses succeed one another in a very narrow time frame through a particular bus system that also transfers the data and further control signals.
In accordance with another feature of the invention, there is provided an address-providing device providing column addresses, at the latest, at an instant tr+Tw, where tr is an instant at which a row address is provided.
In accordance with a further feature of the invention, the address-providing device has means for simultaneously providing a row address and a column address.
In accordance with an added feature of the invention, the address-providing device has an address input with separate input terminals for receiving an externally applied row address and an externally applied column address.
In accordance with an additional feature of the invention, the address-providing device has an address provider simultaneously providing a row address and a column address.
In accordance with yet another feature of the invention, the address-providing device has an address input with separate input terminals for receiving an externally applied row address and an externally applied column address.
In accordance with yet a further feature of the invention, there is provided a first address bus transferring the row addresses and a second address bus transferring the column addresses, the address-providing device being connected to the row decoder through the first address bus and being connected to the column decoder through the second address bus.
In accordance with yet an added feature of the invention, the sense amplifiers have inputs and Tw is equal to a safety time Tb, and Tw elapses starting from an activation of the word line until a signal change, determined by the datum in the memory cells of the relevant row, at the inputs of the associated sense amplifier has reached a level that can be unambiguously discriminated from noise phenomena.
In accordance with yet an additional feature of the invention, the control device has a control signal generator for generating a first control signal for activating the selected word line and for generating a second control signal for connecting the selected sense amplifiers to the data path in accordance with temporal stipulations of an immediate-write execution program activated by the immediate-write command and, in an event of an activation of the immediate-write execution program, causes the control signal generator to generate the second control signal within a time frame Tw less than Tc beginning with activation of the word line.
In accordance with again another feature of the invention, the word lines, the sense amplifiers, the memory cells, the data path, the addressing device and the control device form a synchronous DRAM memory circuit.
In accordance with yet another feature of the invention, the RAM memory circuit is a synchronous DRAM memory circuit
With the objects of the invention in view, there is also provided a method for controlling an operation of writing data into a RAM memory circuit, including the steps of providing a memory circuit having a multiplicity of memory cells disposed in matrix form in rows and columns, the cells storing datum, the rows having row addresses, the columns having column addresses, word lines each being associated with a respective one of the rows, sense amplifiers each being associated with a respective one of the columns, data input/output means, a data path for transferring data in either direction between the input/output means and the sense amplifiers, and each memory cell being addressable for writing in or reading out a datum by activation of the one word line associated with a respective one of the rows and by connecting of a sense amplifier associated with a respective one of the columns to the data path, providing an addressing device having a row decoder connected to the word lines for selecting the word line to be activated dependent upon a provided row address and a column decoder connected to the sense amplifiers for selecting respective ones of the sense amplifiers to be connected to the data path dependent upon the column addresses provided thereto, activating a selected one of the word lines and subsequently initiating a connection of at least one associated selected sense amplifier to the data path, initiating a connection of the selected sense amplifier selected by the column address provided to the data path at an instant ta+Tw, where ta is an instant of an activation of the word line selected by the provided row address and Tw is less than a charging time necessary, starting from the word line activation, to transfer the datum stored in one of the memory cells of the respective one of the rows to the respectively selected sense amplifier and to amplify the datum at the respectively selected sense amplifier.
With the objects of the invention in view, there is also provided a method for controlling an operation of writing data into a RAM memory circuit, including the steps of disposing a multiplicity of memory cells in a matrix of rows and columns, the cells storing datum, the rows having row addresses, the columns having column addresses, associating each of the word lines with a respective one of the rows, associating each of the sense amplifiers with a respective one of the columns, connecting a data path to a data input/output device and to the sense amplifiers for transferring data in either direction between the input/output device and the sense amplifiers, each memory cell being addressable for writing in or reading out a datum by activation of the one word line associated with a respective one of the rows and by connecting of a sense amplifier associated with a respective one of the columns to the data path, connecting a row decoder of an addressing device to the word lines for selecting the word line to be activated dependent upon a provided row address, connecting a column decoder of the addressing device to the sense amplifiers for selecting respective ones of the sense amplifiers to be connected to the data path dependent upon the column addresses provided thereto, selecting one of the word lines by activating the selected word line and subsequently initiating a connection of at least one associated selected sense amplifier to the data path, initiating a connection of the selected sense amplifier selected by the column address provided to the data path at an instant ta+Tw, where ta is an instant of an activation of the word line selected by the provided row address and Tw is less than a charging time necessary, starting from the word line activation, to transfer the datum stored in one of the memory cells of the respective one of the rows to the respectively selected sense amplifier and to amplify the datum at the respectively selected sense amplifier.
In the case of other conventional DRAMs, including the increasingly common xe2x80x9csynchronousxe2x80x9d variants (SDRAMs), the same external terminals (pins) are used for applying the column address bits as for applying the row address bits, in order to keep down the total number of pins. In the case of this customary address multiplex method, first, the row address for the selection of the word line is applied, and only after the valid decoding thereof is there an opportunity for applying one or more successive column addresses for the selection of the memory cells that are to be read from or written to within the selected row (that is to say, for the selection of the sense amplifiers to be connected to the data path). If this address multiplex cannot be accelerated to a sufficient extent to provide the first valid column address early before the charging time Tc has elapsed, separate pins for row and column addressees should, preferably, be provided for the realization of the invention, which allows a simultaneous application of row and column addresses. This can even be realized without significantly increasing the space requirement, by using so-called ball grid arrays in which, in contrast to the currently predominant TSOP housings (which have contact regions at the side), the entire housing underside is occupied by contacts, with the result that a larger number of contacts can be accommodated.
In accordance with again a further feature of the invention, wherein the control device has a command decoder decoding the immediate-write command from externally applied command bits.
In accordance with again an added feature of the invention, the command decoder decodes the immediate-write command from two directly successively applied words of m externally applied command bits in each case.
In accordance with again an additional feature of the invention, there is provided an input for application of an externally generated immediate-write command, the control device having a command decoder activating the immediate-write execution program in the control signal generator upon reception of the externally generated immediate-write command.
In accordance with a concomitant feature of the invention, there is provided an input for application of an externally generated immediate-write command, the input being connected to the control signal generator to activate, upon reception of the externally generated immediate-write command, the immediate-write execution program in the control signal generator.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a RAM memory circuit and method for controlling the RAM memory circuit, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.